The present invention relates to a method and/or architecture for analog signal processing generally and, more particularly, to a method and/or architecture for implementing noise reduction auto phasing sampled data systems in mixed signal integrated circuits.
As integrated circuit integration density continues to increase and signal voltage swings continue to decrease (with decreasing power supply voltages), on-chip signal-to-noise ratio (SNR) is degrading. Noise on an integrated circuit (IC) degrades SNR. Digital noise is typically induced on mixed system ICs by digital core and I/O activity.
To reduce digital noise, a manual phasing adjustment between the digital clock and the analog sampled data system clock is made via inverter delays. Phasing adjustment is complete when minimum noise is coupled into the sampled data system. However, the phasing adjustment is found through trial and error. The manual method of noise reduction is redundant, tedious and does not incorporate all possible sources of on-chip noise or variations in IC processing. Therefore, the manual phase adjustment setting chosen does not maximize SNR.
It would be desirable to minimize digital noise coupling from an integrated circuit (IC) substrate, power supply, and/or routing into the signal path of a sampled data system on a mixed signal IC.
The present invention concerns an apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a control signal in response to an output signal. The control signal may comprise a peak value of the output signal. The second circuit may be configured to generate a phase adjustment signal in response to the control signal. The third circuit may be configured to generate a second clock signal in response to the phase adjustment signal and a first clock signal. The second clock signal may clock the output signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a noise reduction auto phasing circuit for sampled data systems in mixed signal integrated circuits that may (i) automatically adjust a clock phase, (ii) adapt to different digital modes, (iii) reduce a number of digital noise signatures, (iv) eliminate manual characterization, (v) maximize signal-to-noise ratio, and/or (vi) accommodate wafer lot timing spreads.